Single read based soft-decision decoding of non-volatile memory

ABSTRACT

A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs.

CROSS REFERENCE TO RELATED APPLICATIONS

Priority benefit claims for this application are made in the accompanying Application Data Sheet, Request, or Transmittal (as appropriate, if any). To the extent permitted by the type of the instant application, this application incorporates by reference for all purposes the following applications, all commonly owned with the instant application at the time the invention was made:

-   U.S. Non-Provisional Application (13/567,025), filed on even date     herewith, first named inventor Yunxiang W U, and entitled     SOFT-DECISION COMPENSATION FOR FLASH CHANNEL VARIATION; -   U.S. Non-Provisional application (Ser. No. 13/464,433), filed 4 May     2012, first named inventor Earl T COHEN, and entitled ZERO-ONE     BALANCE MANAGEMENT IN A SOLID-STATE DISK CONTROLLER; and -   U.S. Non-Provisional application (Ser. No. 13/533,130) filed 26 Jun.     2012, first named inventor Yingquan W U, and entitled FAST TRACKING     FOR FLASH CHANNELS.

BACKGROUND

1. Field

Advancements in non-volatile storage technology are needed to provide improvements in performance, efficiency, and utility of use.

2. Related Art

Unless expressly identified as being publicly or well known, mention herein of techniques and concepts, including for context, definitions, or comparison purposes, should not be construed as an admission that such techniques and concepts are previously publicly known or otherwise part of the prior art. All references cited herein (if any), including patents, patent applications, and publications, are hereby incorporated by reference in their entireties, whether specifically incorporated or not, for all purposes.

Various aspects of flash memory as used by Solid State Disk (SSD) controllers will now be described in part to establish a technology background and in part to establish antecedents for nomenclature used in the balance of the specification. The minimal size of data readable by the SSD controller from Non-Volatile Memory (NVM) is a “read unit” that is protected by included error correction, such as a Low-Density Parity-Check (LDPC) code. In some contexts, a read unit is referred to as a “codeword”. In some embodiments, each read unit contains approximately 4K to approximately 32K bits of user data, plus error correction overhead. Under command of the SSD controller, those bits are read from NVM memory cells (e.g. via an array access of one or more portions of the NVM memory cells), which depending on the technology as discussed below, may hold one or more bits per cell. In some embodiments, for security reasons an SSD controller encrypts the data prior to writing the data to NVM. In some embodiments, in view of circuit design limitations with respect to long strings of identically programmed cells, an SSD controller scrambles the data prior to writing the data to NVM.

Considered individually, each cell has a particular stored (programmed) charge that corresponds to a device threshold voltage for that cell, and further corresponds to the logical bit values being stored in the cell. While ideally all of the cells in the NVM would have identical device threshold voltages for the logical bit values stored, in practice for a variety of reasons the device threshold voltages differ across the cells in probability distributions along the device threshold voltage axis (e.g., “device threshold voltage distributions”) that are similar to a Gaussian in shape.

Thus considered in aggregate across a large number of cells, such as of a read unit, there are as many device threshold voltage distributions (e.g., Gaussian probability curves) as there are states per cell (two states per bit of storage per cell). That is, for N-bits per cell of storage, there are 2**N states and the same number of device threshold voltage distributions. Generally, (2**N)−1 different read thresholds (read voltage references V_(READ1) through V_(READ(N-1))) are required by read circuits in the NVM to distinguish between the 2**N states.

Continuing from above, for Single-Level Cell (SLC) flash memories, N=1. SLC memories thus store one-bit per cell of storage, have two device threshold voltage distributions (one for zeroes and another for ones), and require a single read threshold, read voltage reference V_(READ1). From lower to higher device threshold voltages, the two device threshold voltage distributions are known as the E (Erased) state and D1 (first Data) state. While arbitrary, a common mapping (coding) is to assign logical one to the E state and logical zero to the D1 state. Thus references to zeroes and ones are proxy references for respective decodings of the D1 state and the E state.

Continuing further from above, for Multi-Level Cell (MLC) flash memories, N>1. MLC memories thus store more than one bit per cell, have more than two device threshold voltage distributions, and require multiple different read thresholds to distinguish the distributions. For example, a 4LC memory (e.g. flash memory) stores two bits per cell, has four device threshold voltage distributions, and generally requires three read thresholds (read voltage references V_(READ1), V_(READ2), and V_(READ3)). From lower to higher device threshold voltages, the four device threshold voltage distributions are known as the E (Erased), D1 (Data1), D2 (Data2), and D3 (Data3) states. While arbitrary, each of the four device threshold voltage distributions is also mapped (addressed) in accordance with a particular binary sequence, such as a Gray code sequence. Thus references to one or more of the 11, 10, 00, and 01 states, are proxy references for respective decodings of the E, D1, D2, and D3 states.

With respect to address mapping used for the states of an MLC, each can be said to have a Most Significant Bit (MSB) and a Least Significant Bit (LSB) (and for more than two bits per cell, bits of significance in between). While there are various ways that MLC NVMs program their cells, the following approach is common. An initial programming round (a manipulation of the charge distributions) establishes the LSB, e.g., writes the “lower pages”. This is done loosely in the same manner as for writing an SLC, e.g., a charge manipulation that establishes the E state device threshold voltage distribution and a second state device threshold voltage distribution. Depending on the binary sequence used, the second state device threshold voltage distribution is similar to the D1 state device threshold voltage distribution, similar to the D2 state device threshold voltage distribution, or between the D1 and D2 state device threshold voltage distributions. For MLC, one or more additional programming rounds further manipulate the device threshold voltage distributions (in number, location along the device threshold voltage axis, and in shape), as required per the number of levels of the MLC. More particularly, one or more subsequent programming operations write the “middle pages” (if any, for more than two bits per cell), and a last programming operation establishes the MSB, e.g., writes the “upper pages”. For example, in a 4LC (2-bit per cell MLC), the E distribution and the second distribution of the first program round are respectively bifurcated by a second program round into E and D1 distributions and D2 and D3 distributions.

The device threshold voltage distributions are modified away from their initial/nominal distributions by one or more factors, such as read disturb, write disturb, and retention loss. More particularly, over time, temperature, and other factors related to use, the location of each of the device threshold voltage distribution can move around with respect to the device threshold voltage axis. Such changes increase the likelihood of read errors that are performed using a read reference voltage value for the read threshold that was previously established based on the nominal device threshold voltage distribution. In some SLC embodiments, when a hard-decision uncorrectable error is encountered in a read unit read from NVM, a series of retry operations is performed to recover the read unit. The retry operations include the controller re-reading the read unit at different voltage values of the read threshold V_(READ1), such as determined by a register setting written via an I/O command from the SSD controller. By reading at different settings of the read threshold V_(READ1), the read unit is sampled at different points on the device threshold voltage axis in an attempt to locate a sample of the read unit that is (hard-decision) correctable.

One algorithm suggested by NVM vendors is sweeping the SLC read threshold slowly upwards (increasing the read reference voltage V_(READ1) from its nominal value) in an attempt to find a sample of the read unit that is correctable. If this procedure fails, then the read threshold is swept in another direction (decreasing the read reference voltage V_(READ1) from its nominal value). If both sweeps fail, then the read unit is uncorrectable (by hard-decision decoding). Linearly sweeping the read threshold, which might have 16 to 64 steps at different respective read reference voltage settings, requires many time-consuming samples of the read unit (each with an attendant recovery time latency). Even when such a search is infrequently required, and thus not a major impact on average latencies, for applications with strict maximum latency requirements, including some database applications, such a time-consuming search is unacceptable.

SYNOPSIS

The invention may be implemented in numerous ways, including as a process, an article of manufacture, an apparatus, a system, a composition of matter, and a computer readable medium such as a computer readable storage medium (e.g., media in an optical and/or magnetic mass storage device such as a disk, or an integrated circuit having non-volatile storage such as flash storage) or a computer network wherein program instructions are sent over optical or electronic communication links. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. The Detailed Description provides an exposition of one or more embodiments of the invention that enable improvements in performance, efficiency, and utility of use in the field identified above. The Detailed Description includes an Introduction to facilitate the more rapid understanding of the remainder of the Detailed Description. The Introduction includes Example Embodiments of one or more of systems, methods, articles of manufacture, and computer readable media in accordance with the concepts described herein. As is discussed in more detail in the Conclusions, the invention encompasses all possible modifications and variations within the scope of the issued claims.

In various embodiments and/or usage scenarios, hard decode errors are resolved by soft decoding. Soft decoding uses techniques enabled to correct errors more robustly (e.g. LDPC) at the cost of additional implementation complexity compared to hard decoding algorithms (e.g. BCH codes). One additional complexity of soft decoding is generating soft-decision metrics. Some techniques generate soft-decision metrics by performing additional reads (e.g. ‘retry reads’) and/or array accesses and calculating soft-decision metrics at least in part based upon the results of the additional reads and/or array accesses.

The inventors believe they are the first to note the significance, with respect to performance, power, cost and/or reliability, the benefits of generating soft-decision metrics from a hard decode read in an NVM controller. More particularly, the inventors believe they are the first to note that channel parameters (e.g. charge distributions, and device threshold voltages) from hard decoding enable generating soft-decision metrics without additional reads and/or array accesses. Eliminating additional reads and/or array accesses reduces one or more of latency, power consumption, and bandwidth costs associated with soft decoding, and enables more efficient soft decoding of otherwise uncorrectable (e.g. hard decoding) errors.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A illustrates selected details of an embodiment of a Solid-State Disk (SSD) including an SSD controller that implements optimization of read thresholds for managing Non-Volatile Memory (NVM) elements (e.g., flash memories).

FIG. 1B illustrates selected details of various embodiments of systems including one or more instances of the SSD of FIG. 1A.

FIGS. 2A and 2B illustrate example device threshold voltage distributions relevant to decoding of an NVM, specifically respectively for SLC and MLC memories.

FIG. 3 illustrates selected details of a system embodiment of an instance of the SSD of FIG. 1A, providing particular details regarding decoding of an NVM.

FIG. 4 illustrates a flow diagram of selected details of an embodiment of single-read based soft-decision decoding of NVM.

List of Reference Symbols in Drawings Ref. Symbol Element Name 100 SSD Controller 101 SSD 102 Host 103 (optional) Switch/Fabric/Intermediate Controller 104 Intermediate Interfaces 105 OS 106 FirmWare (FW) 107 Driver 107D dotted-arrow (Host Software ←→ I/O Device Communication) 109 Application 109D dotted-arrow (Application ←→ I/O Device Communication via driver) 109V dotted-arrow (Application ←→ I/O Device Communication via VF) 110 External Interfaces 111 Host Interfaces 112C (optional) Card Memory 113 Tag Tracking 114 Multi-Device Management Software 115 Host Software 116 I/O Card 117 I/O & Storage Devices/Resources 118 Servers 119 LAN/WAN 121 Data Processing 123 Engines 131 Buffer 133 DMA 135 ECC-X 137 Memory 141 Map 143 Table 151 Recycler 161 ECC 171 CPU 172 CPU Core 173 Command Management 175 Buffer Management 177 Translation Management 179 Coherency Management 180 Memory Interface 181 Device Management 182 Identity Management 190 Device Interfaces 191 Device Interface Logic 192 Flash Device 193 Scheduling 194 Flash Die 199 NVM 210 SLC Nominal Read Threshold 220 SLC Nominal Most-Negative Threshold State 230 SLC Nominal Most-Positive Threshold State 240 MLC Nominal First Read Threshold 242 MLC Nominal Second Read Threshold 244 MLC Nominal Third Read Threshold 250 MLC Nominal Most-Negative Threshold State 260 MLC Nominal Next-Most-Negative Threshold State 270 MLC Nominal Next-Most-Positive Threshold State 280 MLC Nominal Most-Positive Threshold State 306 Write Data 310 Scrambler 311 Scrambled Write Data 320 ECC/LDPC Encoder 321 ECC Encoded Write Data 332 NVM Array 334 Programmable Read Voltage Circuitry 336 Control/Status Registers 338 I/O 340 Channel Parameter Estimator 341 Parameters 351 Read Data 359 Uncorrected & Scrambled (Raw) Read Data 360 ECC/LDPC Decoder 361 Corrected Read Data 362 Soft Metrics 370 Descrambler 371 Unscrambled Read Data 380 Soft Metric Converter 410 Read NVM Location 420 Hard Decode Raw Read Data 430 Read Error Evaluation 440 Generate Soft-Decision Metrics 450 Channel Parameters 460 Soft Decode Raw Read Data Based on Soft-Decision Metrics

DETAILED DESCRIPTION

A detailed description of one or more embodiments of the invention is provided below along with accompanying figures illustrating selected details of the invention. The invention is described in connection with the embodiments. The embodiments herein are understood to be merely exemplary, the invention is expressly not limited to or by any or all of the embodiments herein, and the invention encompasses numerous alternatives, modifications, and equivalents. To avoid monotony in the exposition, a variety of word labels (including but not limited to: first, last, certain, various, further, other, particular, select, some, and notable) may be applied to separate sets of embodiments; as used herein such labels are expressly not meant to convey quality, or any form of preference or prejudice, but merely to conveniently distinguish among the separate sets. The order of some operations of disclosed processes is alterable within the scope of the invention. Wherever multiple embodiments serve to describe variations in process, method, and/or program instruction features, other embodiments are contemplated that in accordance with a predetermined or a dynamically determined criterion perform static and/or dynamic selection of one of a plurality of modes of operation corresponding respectively to a plurality of the multiple embodiments. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. The details are provided for the purpose of example and the invention may be practiced according to the claims without some or all of the details. For the purpose of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

Introduction

This introduction is included only to facilitate the more rapid understanding of the Detailed Description; the invention is not limited to the concepts presented in the introduction (including explicit examples, if any), as the paragraphs of any introduction are necessarily an abridged view of the entire subject and are not meant to be an exhaustive or restrictive description. For example, the introduction that follows provides overview information limited by space and organization to only certain embodiments. There are many other embodiments, including those to which claims will ultimately be drawn, discussed throughout the balance of the specification.

Acronyms

At least some of the various shorthand abbreviations (e.g. acronyms) defined here refer to certain elements used herein.

Acronym Description AES Advanced Encryption Standard AHCI Advanced Host Controller Interface API Application Program Interface ASCII American Standard Code for Information Interchange ATA Advanced Technology Attachment (AT Attachment) BCH Bose Chaudhuri Hocquenghem BER Bit Error Rate CD Compact Disk CF Compact Flash CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit CRC Cyclic Redundancy Check DAS Direct Attached Storage DDR Double-Data-Rate DES Data Encryption Standard DMA Direct Memory Access DNA Direct NAND Access DRAM Dynamic Random Access Memory DVD Digital Versatile/Video Disk DVR Digital Video Recorder ECC Error-Correcting Code eMMC Embedded MultiMediaCard eSATA external Serial Advanced Technology Attachment GPS Global Positioning System HDD Hard Disk Drive I/O Input/Output IC Integrated Circuit IDE Integrated Drive Electronics JPEG Joint Photographic Experts Group LAN Local Area Network LB Logical Block LBA Logical Block Address LDPC Low-Density Parity-Check LFSR Linear Feedback Shift Register LPN Logical Page Number LSB Least Significant Bit LZ Lempel-Ziv MLC Multi-Level Cell MMC MultiMediaCard MPEG Moving Picture Experts Group MSB Most Significant Bit NAS Network Attached Storage NCQ Native Command Queuing NVM Non-Volatile Memory ONA Optimized NAND Access ONFI Open NAND Flash Interface OS Operating System PC Personal Computer PCIe Peripheral Component Interconnect express (PCI express) PDA Personal Digital Assistant PHY PHYsical interface POS Point Of Sale RAID Redundant Array of Inexpensive/Independent Disks RASIE Redundant Array of Silicon Independent Elements ReRAM Resistive Random Access Memory RS Reed-Solomon RSA Rivest, Shamir & Adleman SAN Storage Attached Network SAS Serial Attached Small Computer System Interface (Serial SCSI) SATA Serial Advanced Technology Attachment (Serial ATA) SCSI Small Computer System Interface SD Secure Digital SDR Single-Data-Rate SLC Single-Level Cell SMART Self-Monitoring Analysis and Reporting Technology SSD Solid-State Disk/Drive TCG Trusted Computing Group UFS Unified Flash Storage USB Universal Serial Bus VF Virtual Function WAN Wide Area Network Tracking and Restoring Zero/One Balances

The initial discussion that follows, of tracking and managing counts for zeroes and ones and the shifting of the read threshold used to distinguish the zero and one states, is directly applicable to SLC memories and (with minor variation, as noted) to the lower pages of MLC memories. More generally with respect to MLC memories, extension to tracking and managing counts for upper pages and the shifting of multiple read thresholds (e.g., read voltage references V_(READ1), V_(READ2), and V_(READ3)) is detailed in separate paragraphs below.

In some embodiments, a zero count and a one count are obtained for each read unit (or each group of read units transferred at one time from one NVM die) read from an SLC NVM. In an event that the read unit is uncorrectable (e.g. in a context of hard-decision decoding) in part due to the shift in the device threshold voltage distributions away from their (initial) nominal distributions, the zero count and/or the one count enable a determination of a direction and/or a magnitude to move (set) a read threshold to track the shift in the device threshold voltage distributions and restore the zero/one balance. The read threshold being adjusted is read voltage reference V_(READ1) for SLC memories and read voltage reference V_(READ2) for the lower pages of MLC memories. For example, in an SLC having a logical one assigned to the erase state, and written with a known statistically equal (50-50 percent, a.k.a. 50/50 percent, or simply 50/50) distribution of zeroes and ones, if a current zero/one counts indicates a predominance of ones, V_(READ1) is shifted lower; and if the current zero/one counts indicates a predominance of zeroes, V_(READ1) is shifted higher. (Substitute V_(READ2) for V_(READ1) in the foregoing example, for the lower pages of MLC memories.) A magnitude of how much to change (shift) the read threshold is optionally determined by a percentage of a number of zeroes (or ones). The magnitude is based on one or more of: the number of zeroes and/or ones observed in one or more samples; a read threshold increment of the one or more samples; a knowledge of predicted device threshold voltage distributions corresponding to a midpoint between the peaks of the two distributions; program/erase count (wear); read disturb counts; retention time; and other similar factors.

Finding the Read-Equilibrium Point

In further embodiments, a binary-search-like operation (iteratively sampling the same read unit at respective values of the appropriate read voltage reference) is used to find a read threshold “read-equilibrium point”. This is a point on the device threshold voltage axis between adjacent device threshold voltage distributions resulting in raw data (pre error correction) statistical state distributions that upon reading, match within a statistical margin of error to the statistical state distributions written, or idealized models of same.

For SLC memory and random scrambling, such as resulting from encryption, the read-equilibrium point is the read threshold (read voltage reference V_(READ1)) where a zero/one balance (of the raw data read from the NVM) is most even (near identical). Under such conditions, the two state distributions have a 50-50 balance. I.e., 50% of the states read are zeroes and 50% of the states read are ones. (Substitute V_(READ2) for V_(READ1) in the foregoing for the lower pages of MLC memories.)

In some embodiments, the read-equilibrium point corresponds to one or more of: a center point between two voltage distributions, a minima between two voltage distributions, a point at which the zero/one balance in read data is closest to 50-50, and a point determined according to interpolation of the zero/one balance found at two other points. The read equilibrium point corresponds to a center-point between the adjacent device threshold voltage distributions in embodiments having symmetric adjacent device threshold voltage distributions.

Finding and setting the read threshold to the desired read-equilibrium point reduces the number of reads required to find an optimal point at which to attempt hard-decision decoding. In still further embodiments, hard-decision decoding is attempted at each read threshold sampling point (each value of V_(READ1) for SLC memories, or each value of V_(READ2) for the lower pages of MLC memories) in the binary search in the event a “good enough” read threshold is found before the read threshold read-equilibrium point is found. The search is generally truncated upon finding the good enough read threshold, except as discussed below regarding possibly taking additional sampling around the determined read-equilibrium point for soft-decision decoding purposes. In various embodiments, the “good enough” read threshold results in successful hard decision decoding of the raw read data. In some embodiments, a magnitude of the search steps (the read threshold increment) in the binary search is determined (based), at least in part, on various factors as detailed above regarding the magnitude of the read threshold change.

MLC Considerations

In MLC memories, multiple read thresholds are managed. In some embodiments, this is performed by assuming uniform displacements of the multiple device-threshold-voltage distributions and changing all other read thresholds based on decisions made for the first read threshold (V_(READ1)) based on a read data zero/one balance of the lower pages.

For a 4LC NVM, theoretically there is a 11/10/00/01 balance of 25-25-25-25 (in contrast to a zero/one balance of 50-50). However, there is no single operation that directly provides this balance, given that 4LCs are generally read via separate array accesses using the three read voltage references: V_(READ2) for lower pages and V_(READ1) and V_(READ3) for upper pages. One could thus evaluate two respective zero/one balances: between the D1 and D2 states for lower pages, and between the E and D1 states combined with between the D2 and D3 states for upper pages. Alternatively, one could carry out three separate lower-page-like array accesses setting the single lower-page read threshold to values near each of V_(READ1), V_(READ2), and V_(READ3).

By way of example, in some 4LC NVM embodiments, read voltage references V_(READ1), V_(READ2), and V_(READ3) may need shifting, at least for one of the two bits stored in the cell. Working similarly to the SLC case, one of the two bits stored in the cell requires a single array access at a first read threshold (V_(READ2), in this MLC case). Ascertaining the other bit requires two additional read thresholds (V_(READ1), and V_(READ3), and effectively two associated respective additional array accesses that are performed internally by the NVM).

According to various embodiments, either: the two read thresholds (V_(READ1) and V_(READ3)) for the other bit are moved in unison by a same and/or a differing amount (under a presumption that drift is similar for both states); or the two read thresholds for the other bit are moved independently (at a cost in additional read operations). The latter option requires knowing the state of the SLC-like bit in the cell (the LSB), as the state of the SLC-like bit determines which of the two read thresholds (V_(READ1) and V_(READ3)) are used for ascertaining the corresponding other bit (the MSB).

In some 4LC embodiments, a combined “upper page” read data zero/one balance is evaluated for a simultaneous blend of the E and D1 distributions and the D2 and D3 distributions. Based on disparities in the combined zero/one balance read vs. that written, and in view of the bit sense reversal (1 to 0 for moving from E to D1, and 0 to 1 for moving from D2 to D3), the corresponding two read thresholds (V_(READ1) and V_(READ3)) are moved in unison in opposite directions. This is done such that the zero/one balance of each component of the blend moves “in the same direction” (e.g., the movements do not conflict).

In some 4LC embodiments, the movement of the two upper page read thresholds (V_(READ1) and V_(READ3)) are separately determined by respective evaluations of zero/one balance for the upper page while using a respective LSB for each bit of the read unit. When the LSB=1, the direction of movement is the opposite of that of the LSB=0 case. For example, instead of computing a disparity between a zero count and a one count in upper page read data, an upper page disparity is computed by selectively modifying each bit of upper page read data based on a corresponding bit of lower page read data, converting a sense of the bits of the upper page read data from a numeric value to a directional value where, for example, 0 represents a higher device threshold voltage and 1 represents a lower device threshold voltage. In some embodiments, an XNOR of the bits of the upper page read data and the corresponding bits of the lower page read data performs the converting.

Removing Bias from Soft-Decision Samples

In some embodiments, soft decision information is obtained from NVM to perform soft-decision based decoding. The soft decision information is obtained by reading a read unit (or each group of read units transferred at one time from one NVM die) at a variety of read threshold sampling points (for an SLC, values of V_(READ1)) about the nominal (unadjusted) read threshold to obtain multiple samples of data of the read unit, thus building up a soft-decision likelihood of a value of each bit of the read unit. A spacing of the samples depends, at least in part, on particular properties of the NVM used, such as its nominal separation of charge states.

The soft-decision information is biased, however, unless the nominal read threshold about which the samples are taken is a read threshold read-equilibrium point (as described above). If the current read threshold is not the threshold read-equilibrium point, then all the soft-decision information is biased in one direction or the other. Following are two example techniques to adjust for this and obtain unbiased (or at least less-biased) soft-decision information:

-   -   1. Since a zero/one balance of the read unit as sampled at each         of the read threshold sampling points is readily identified, the         read threshold read-equilibrium point is readily determined         (according to embodiment, such as by using linear         interpolation). An offset is calculated corresponding to the         difference between the determined read threshold         read-equilibrium point and the (old, unadjusted) nominal read         threshold. Previously determined soft-decision information is         enabled to be properly “re-centered” and still used by applying         the offset with respect to the voltages at which the         soft-decision information was previously sampled (with values         larger than 1.0 or less than 0.0 being truncated). This approach         requires no additional reads, but produces a differing amount of         precision/accuracy for some of the data.     -   2. Since a zero/one balance of the read unit as sampled at each         of the read threshold sampling points is readily identified,         after collecting all required samples, the read threshold         sampling point closest to the read threshold read-equilibrium         point is readily determined. The closest is the read threshold         sampling point with the zero/one balance most proximate to the         zero/one balance written. For the SLC encryption (or scrambling)         case, it is the read threshold sampling point closest to having         a 50-50 balance. As all of the samples nominally have equivalent         spacing from each other, the closest sample is chosen as a new         nominal read threshold, and additional soft-decision information         samples are optionally gathered (assuming the new nominal read         threshold differs from the old). Alternatively, a binary search         to find the threshold read-equilibrium point is done first, with         precision of the binary search limited to a finest granularity         of sampling required for the desired precision of the         soft-decision information. The desired precision of the         soft-decision information has an associated sample window around         the new nominal read threshold. Doing a binary search as a part         of multiple reads needed to obtain soft-decision information         requires no additional reads, unless the old nominal read         threshold falls outside the desired precision sample window.

In the SLC encryption embodiments described so far, the above techniques have focused on finding a preferred read threshold that yields a read data zero/one balance that is closest to 50-50. For cases where the device threshold voltage distributions are of generally the same symmetric shape and do not substantively overlap, this preferred read threshold would also correspond to the minima of the combined device threshold voltage distributions.

Read Threshold Interpolated from Known Points on the Device Threshold Voltage Distributions

In some embodiments, another approach to finding the preferred read threshold is to instead find two points, one on each adjacent device threshold voltage distribution, and determine the midpoint between these two points by interpolation. For example, sampling at the peak of each device threshold voltage distribution should yield a 75/25 balance of read data zeroes/ones (or ones/zeroes, depending on which peak). Once the two peaks are identified, the calculated midpoint between the two on the device threshold voltage axis is used to set a new read threshold.

If it is known a priori that the device threshold voltage distributions are not uniform (e.g., asymmetrically biased on one side or the other, such as by having a long tail), then in some embodiments that information is used to interpret the position of the peak and to locate the center by a slightly more complex interpolation (e.g., not just the midpoint). Factors such as retention time and/or wear may influence the symmetry of the device threshold voltage distributions and are accounted for in some embodiments. Multiple sampling points are also used in some embodiments to reveal the shape of the device threshold voltage distributions.

In some embodiments where the range of device threshold voltage adjustment is limited, it may not be possible to find the true peak. In particular, the device threshold voltage cannot be moved less than 0V with some flash devices even though the voltage distribution of the E state extends into negative device threshold voltages. Knowledge of the device threshold voltage distribution still permits the midpoint to be determined via interpolation. For example, if at 0V the read data zero/one balance is 60/40, then approximately 10% excess zeroes are being observed and an area of the E distribution to the right of 0V is approximately 10%. In a first approach of some embodiments, the peak of the D1 distribution is found, and the midpoint is interpolated based on knowledge of the approximate shape of the E distribution. In a second approach of some embodiments, the point of the D1 distribution at which the read data zero/one balance is 40/60 (the opposite point from the 0V measurement) is found. The calculated midpoint between the 60/40 and the 40/60 observations is then used to set the new preferred read threshold. The calculated midpoint could be determined with greater precision with additional knowledge and/or measurement of the two device threshold voltage distributions.

In some embodiments, the points being interpolated are both on a same side as the read equilibrium point. For example, knowing that a first read threshold sampling point X yields 75/25 read data zero/one balance and a second read threshold sampling point Y yields 62.5/37.5, the read equilibrium point would be close to Y+/−(X-Y) where ‘+’ vs. ‘−’ depends on whether Y is less than X. The direction of the read equilibrium point is the direction corresponding to moving the read data zero/one balance closer to 50/50. In the example given, that is in the direction from X and toward Y. Knowledge of the device threshold voltage distributions would yield a more accurate interpolation rather than the simple linear interpolation indicated.

Single-Read Based Soft-Decision Decoding of Non-Volatile Memory

In various embodiments, a Solid-State Disk (SSD) controller is enabled to perform hard-decision decoding and soft-decision decoding of reads of a Non-Volatile Memory (NVM). In some scenarios, hard-decision decoding is advantageous, e.g. having lower latency and/or power consumption with relatively simpler algorithms than soft-decision decoding. However, in some scenarios, soft-decision decoding uses relatively more complex algorithms (e.g. LDPC) that achieve higher error correction capabilities than hard-decision decoding. In some embodiments, an SSD controller reads a location using hard-decision decoding; if an error occurs, then the controller reads the location again using soft-decision decoding.

In some SSD controllers, soft-decision decoding requires additional reads of the NVM (i.e. separate from the reads used for hard-decision decoding). In some embodiments, the SSD controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. The controller performs soft decoding using the generated soft-decision metrics. Using a single read to perform soft-decision decoding enables one or more of lower latency, higher reliability and lower power consumption.

Example Embodiments

In concluding the introduction to the detailed description, what follows is a collection of example embodiments, including at least some explicitly enumerated as “ECs” (Example Combinations), providing additional description of a variety of embodiment types in accordance with the concepts described herein; these examples are not meant to be mutually exclusive, exhaustive, or restrictive; and the invention is not limited to these example embodiments but rather encompasses all possible modifications and variations within the scope of the issued claims and their equivalents.

EC1) A method comprising:

-   -   in a controller enabled to operate with a Non-Volatile Memory         (NVM), using information from solely a single read of a location         of the NVM to generate soft-decision metrics; and     -   performing soft-decision decoding to determine contents of the         location based at least in part on the generated soft-decision         metrics.

EC2) The method of EC1, wherein the NVM comprises an NVM array, the NVM array comprises a flash memory array, and the location is in the flash memory array.

EC3) The method of EC1, wherein the location is operated in accordance with a Single-Level Cell (SLC) technique and the single read corresponds to a single array access of at least the location in accordance with a single read threshold.

EC4) The method of EC3, wherein the channel parameters are particular channel parameters, various channel parameters comprise the particular channel parameters and one or more other channel parameters, and further comprising computing the various channel parameters as respective channel parameters for each of a plurality of regions of the NVM, the location being in a particular one of the regions.

EC5) The method of EC3, wherein the single read threshold is an operating threshold.

EC6) The method of EC1, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.

EC7) The method of EC6, wherein the MLC technique provides four discrete states.

EC8) The method of EC6, wherein the MLC technique provides eight discrete states.

EC9) The method of EC6, wherein the respective read thresholds are operating read thresholds.

EC10) The method of EC1, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.

EC11) The method of EC10, wherein the controller estimates the device threshold voltage distributions.

EC12) The method of EC10, wherein the location is operated in accordance with a Single-Level Cell (SLC) technique, the single read corresponds to a single array access of at least the location in accordance with a single read threshold, and the single read threshold is a new operating read threshold.

EC13) The method of EC10, wherein the particular location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, the single read corresponds to less than N array accesses at least the location, each of the array accesses is in accordance with a respective read threshold, and one or more of the respective read thresholds are new operating read thresholds.

EC14) The method of EC1, wherein the single read is in response to a request from a host received via a host interface of the controller, and the host interface is compatible with at least one storage interface standard.

EC15) The method of EC1, wherein the NVM comprises at least one flash memory and the single read is communicated by the controller to the at least one flash memory via a flash memory interface.

EC16) The method of EC1, wherein the NVM comprises at least one flash memory.

EC17) The method of EC1, wherein the controller comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a Solid State Disk (SSD).

EC18) The method of EC1, wherein the controller comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a single Integrated Circuit (IC).

EC19) A system comprising:

-   -   means for using information from solely a single read of a         location of a Non-Volatile Memory (NVM) to generate         soft-decision metrics; and     -   means for performing soft-decision decoding to determine         contents of the location based at least in part on the generated         soft-decision metrics.

EC20) The system of EC19, wherein the NVM comprises an NVM array, the NVM array comprises a flash memory array, and the location is in the flash memory array.

EC21) The system of EC19, wherein the location is operated in accordance with a Single-Level Cell (SLC) technique and the single read corresponds to a single array access of at least the location in accordance with a single read threshold.

EC22) The system of EC21, wherein the single read threshold is an operating threshold.

EC23) The system of EC19, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.

EC24) The system of EC23, wherein the MLC technique provides four discrete states.

EC25) The system of EC23, wherein the MLC technique provides eight discrete states.

EC26) The system of EC23, wherein the respective read thresholds are operating read thresholds.

EC27) The system of EC19, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.

EC28) The system of EC27, wherein the channel parameters are particular channel parameters, various channel parameters comprise the particular channel parameters and one or more other channel parameters, and further comprising means for computing the various channel parameters as respective channel parameters for each of a plurality of regions of the NVM, the location being in a particular one of the regions.

EC29) The system of EC27, further comprising means for estimating the device threshold voltage distributions.

EC30) The system of EC27, wherein the location is operated in accordance with a Single-Level Cell (SLC) technique, the single read corresponds to a single array access of at least the location in accordance with a single read threshold, and the single read threshold is a new operating read threshold.

EC31) The system of EC27, wherein the particular location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, the single read corresponds to less than N array accesses at least the location, each of the array accesses is in accordance with a respective read threshold, and one or more of the respective read thresholds are new operating read thresholds.

EC32) The system of EC19, wherein the single read is in response to a request from a host received via a host interface that is compatible with at least one storage interface standard.

EC33) The system of EC19, wherein the NVM comprises at least one flash memory and the single read is communicated to the at least one flash memory via a flash memory interface.

EC34) The system of EC19, wherein the NVM comprises at least one flash memory.

EC35) The system of EC19, further comprising:

-   -   a host interface that is compatible with at least one storage         interface standard and enabled to communicate with a host;     -   a flash memory interface enabled to communicate with at least         one flash memory of the NVM; and     -   wherein the means for using, the means for performing, the host         interface, and the flash memory interface are comprised in a         Solid State Disk (SSD).

EC36) The system of EC19, further comprising:

-   -   a host interface that is compatible with at least one storage         interface standard and enabled to communicate with a host; and     -   a flash memory interface enabled to communicate with at least         one flash memory of the NVM; and     -   wherein the means for using, the means for performing, the host         interface, and the flash memory interface are comprised in a         single Integrated Circuit (IC).

EC37) Any of the foregoing ECs having or referring to a storage interface standard, wherein the storage interface standard comprises one or more of

-   -   a Universal Serial Bus (USB) interface standard,     -   a Compact Flash (CF) interface standard,     -   a MultiMediaCard (MMC) interface standard,     -   an embedded MMC (eMMC) interface standard,     -   a Thunderbolt interface standard,     -   a UFS interface standard,     -   a Secure Digital (SD) interface standard,     -   a Memory Stick interface standard,     -   an xD-picture card interface standard,     -   an Integrated Drive Electronics (IDE) interface standard,     -   a Serial Advanced Technology Attachment (SATA) interface         standard,     -   an external SATA (eSATA) interface standard,     -   a Small Computer System Interface (SCSI) interface standard,     -   a Serial Attached Small Computer System Interface (SAS)         interface standard,     -   a Fibre Channel interface standard,     -   an Ethernet interface standard, and     -   a Peripheral Component Interconnect express (PCIe) interface         standard.

EC38) Any of the foregoing ECs having or referring to a flash memory interface, wherein the flash memory interface is compatible with one or more of

-   -   an Open NAND Flash Interface (ONFI),     -   a Toggle-mode interface,     -   a Double-Data-Rate (DDR) synchronous interface,     -   a DDR2 synchronous interface;     -   a synchronous interface, and     -   an asynchronous interface.

EC39) Any of the foregoing ECs having or referring to a host, wherein the host comprises one or more of

-   -   a computer,     -   a workstation computer,     -   a server computer,     -   a storage server,     -   a Storage Attached Network (SAN),     -   a Network Attached Storage (NAS) device,     -   a Direct Attached Storage (DAS) device,     -   a storage appliance,     -   a Personal Computer (PC),     -   a laptop computer,     -   a notebook computer,     -   a netbook computer,     -   a tablet device or computer,     -   an ultrabook computer,     -   an electronic reading device (an e-reader),     -   a Personal Digital Assistant (PDA),     -   a navigation system,     -   a (handheld) Global Positioning System (GPS) device,     -   an automotive control system,     -   an automotive media control system or computer,     -   a printer, copier or fax machine or all-in-one device,     -   a Point Of Sale POS device,     -   a cash-register,     -   a media player,     -   a television,     -   a media recorder,     -   a Digital Video Recorder (DVR),     -   a digital camera,     -   a cellular handset,     -   a cordless telephone handset, and     -   an electronic game.

EC40) Any of the foregoing ECs having or referring to a at least one flash memory, wherein at least a portion of the at least one flash memory comprises one or more of

-   -   NAND flash technology storage cells, and     -   NOR flash technology storage cells.

EC41) Any of the foregoing ECs having or referring to a at least one flash memory, wherein at least a portion of the at least one flash memory comprises one or more of

-   -   Single-Level Cell (SLC) flash technology storage cells, and     -   Multi-Level Cell (MLC) flash technology storage cells.

EC42) Any of the foregoing ECs having or referring to a at least one flash memory, wherein at least a portion of the at least one flash memory comprises one or more of

-   -   polysilicon technology-based charge storage cells, and     -   silicon nitride technology-based charge storage cells.

EC43) Any of the foregoing ECs having or referring to a at least one flash memory, wherein at least a portion of the at least one flash memory comprises one or more of

-   -   two-dimensional technology-based flash memory technology, and     -   three-dimensional technology-based flash memory technology.         System

In some embodiments, an I/O device, such as an SSD, includes an SSD controller. The SSD controller acts as a bridge between the host interface and NVM of the SSD, and executes commands of a host protocol sent from a computing host via a host interface of the SSD. At least some of the commands direct the SSD to write and read the NVM with data sent from and to the computing host, respectively. In further embodiments, the SSD controller is enabled to use a map to translate between LBAs of the host protocol and physical storage addresses in the NVM. In further embodiments, at least a portion of the map is used for private storage (not visible to the computing host) of the I/O device. For example, a portion of the LBAs not accessible by the computing host is used by the I/O device to manage access to logs, statistics, or other private data.

In some embodiments, accessing compressed data of varying-sized quanta in NVM provides improved storage efficiency in some usage scenarios. For example, an SSD controller receives (uncompressed) data from a computing host (e.g., relating to a disk write command), compresses the data, and stores the compressed data into flash memory. In response to a subsequent request from the computing host (e.g., relating to a disk read command), the SSD controller reads the compressed data from the flash memory, uncompresses the compressed data, and provides the uncompressed data to the computing host. The compressed data is stored in the flash memory according to varying-sized quanta, the quanta size varying due to, e.g., compression algorithm, operating mode, and compression effectiveness on various data. The SSD controller uncompresses the data in part by consulting an included map table to determine where header(s) are stored in the flash memory. The SSD controller parses the header(s) obtained from the flash memory to determine where appropriate (compressed) data is stored in the flash memory. The SSD controller uncompresses the appropriate data from the flash memory to produce the uncompressed data to provide to the computing host. In the instant application, uncompress (and variants thereof) is synonymous with decompress (and variants thereof).

In various embodiments, an SSD controller includes a host interface for interfacing with a computing host, an interface for interfacing with NVM such as flash memory, and circuitry for controlling the interfaces and performing (and/or controlling various aspects of the performing) compressing and uncompressing, as well as lower-level error correction, higher-level error correction, and dynamic higher-level redundancy mode management with independent silicon elements.

According to various embodiments, some host interfaces are compatible with one or more of a USB interface standard, a CF interface standard, an MMC interface standard, an eMMC interface standard, a Thunderbolt interface standard, a UFS interface standard, an SD interface standard, a Memory Stick interface standard, an xD-picture card interface standard, an IDE interface standard, a SATA interface standard, a SCSI interface standard, a SAS interface standard, and a PCIe interface standard. According to various embodiments, the computing host is all or any portions of a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, a netbook computer, a tablet device or computer, an ultrabook computer, an electronic reading device (such as an e-reader), a PDA, a navigation system, a (handheld) GPS device, an automotive control system, an automotive media control system or computer, a printer, copier or fax machine or all-in-one device, a POS device, a cash-register, a media player, a television, a media recorder, a DVR, a digital camera, a cellular handset, a cordless telephone handset, and an electronic game. In some embodiments, an interfacing host (such as an SAS/SATA bridge) operates as a computing host and/or as a bridge to a computing host.

In various embodiments, the SSD controller includes one or more processors. The processors execute firmware to control and/or perform operation of the SSD controller. The SSD controller communicates with the computing host to send and receive commands and/or status as well as data. The computing host executes one or more of an operating system, a driver, and an application. Communication by the computing host with the SSD controller is optionally and/or selectively via the driver and/or via the application. In a first example, all communication to the SSD controller is via the driver, and the application provides higher-level commands to the driver that the driver translates into specific commands for the SSD controller. In a second example, the driver implements a bypass mode and the application is enabled to send specific commands to the SSD controller via the driver. In a third example, a PCIe SSD controller supports one or more Virtual Functions (VFs), enabling an application, once configured, to communicate directly with the SSD controller, bypassing the driver.

According to various embodiments, some SSDs are compatible with form-factors, electrical interfaces, and/or protocols used by magnetic and/or optical non-volatile storage, such as HDDs, CD drives, and DVD drives. In various embodiments, SSDs use various combinations of zero or more parity codes, zero or more RS codes, zero or more BCH codes, zero or more Viterbi or other trellis codes, and zero or more LDPC codes.

FIG. 1A illustrates selected details of SSD 101 including SSD Controller 100 that implements optimization of read thresholds (e.g. via zero/one balance management and/or offline tracking techniques) for managing Non-Volatile Memory (NVM) elements (e.g., flash memories). SSD Controller 100 is communicatively coupled via one or more External Interfaces 110 to a host (such as host 102 of FIG. 1B). According to various embodiments, External Interfaces 110 are one or more of: a SATA interface; a SAS interface; a PCIe interface; a Fibre Channel interface; an Ethernet Interface (such as 10 Gigabit Ethernet); a non-standard version of any of the preceding interfaces; a custom interface; or any other type of interface used to interconnect storage and/or communications and/or computing devices. For example, in some embodiments, SSD Controller 100 includes a SATA interface and a PCIe interface.

SSD Controller 100 is further communicatively coupled via one or more Device Interfaces 190 to NVM 199 including one or more storage devices, such as one or more of Flash Device 192. According to various embodiments, Device Interfaces 190 are one or more of: an asynchronous interface; a synchronous interface; a single-data-rate (SDR) interface; a double-data-rate (DDR) interface; a DRAM-compatible DDR or DDR2 synchronous interface; an ONFI compatible interface, such as an ONFI 2.2 or ONFI 3.0 compatible interface; a Toggle-mode compatible flash interface; a non-standard version of any of the preceding interfaces; a custom interface; or any other type of interface used to connect to storage devices.

Each Flash Device 192 has, in some embodiments, one or more individual Flash Die 194. According to type of a particular one of Flash Device 192, a plurality of Flash Die 194 in the particular Flash Device 192 is optionally and/or selectively accessible in parallel. Flash Device 192 is merely representative of one type of storage device enabled to communicatively couple to SSD Controller 100. In various embodiments, any type of storage device is usable, such as an SLC NAND flash memory, MLC NAND flash memory, NOR flash memory, flash memory using polysilicon or silicon nitride technology-based charge storage cells, two- or three-dimensional technology-based flash memory, read-only memory, static random access memory, dynamic random access memory, ferromagnetic memory, phase-change memory, racetrack memory, ReRAM, or any other type of memory device or storage medium.

According to various embodiments, Device Interfaces 190 are organized as: one or more busses with one or more of Flash Device 192 per bus; one or more groups of busses with one or more of Flash Device 192 per bus, where busses in a group are generally accessed in parallel; or any other organization of one or more of Flash Device 192 onto Device Interfaces 190.

Continuing in FIG. 1A, SSD Controller 100 has one or more modules, such as Host Interfaces 111, Data Processing 121, Buffer 131, Map 141, Recycler 151, ECC 161, Device Interface Logic 191, and CPU 171. The specific modules and interconnections illustrated in FIG. 1A are merely representative of one embodiment, and many arrangements and interconnections of some or all of the modules, as well as additional modules not illustrated, are conceived. In a first example, in some embodiments, there are two or more Host Interfaces 111 to provide dual-porting. In a second example, in some embodiments, Data Processing 121 and/or ECC 161 are combined with Buffer 131. In a third example, in some embodiments, Host Interfaces 111 is directly coupled to Buffer 131, and Data Processing 121 optionally and/or selectively operates on data stored in Buffer 131. In a fourth example, in some embodiments, Device Interface Logic 191 is directly coupled to Buffer 131, and ECC 161 optionally and/or selectively operates on data stored in Buffer 131.

Host Interfaces 111 sends and receives commands and/or data via External Interfaces 110, and, in some embodiments, tracks progress of individual commands via Tag Tracking 113. For example, the commands include a read command specifying an address (such as an LBA) and an amount of data (such as a number of LBA quanta, e.g., sectors) to read; in response the SSD provides read status and/or read data. For another example, the commands include a write command specifying an address (such as an LBA) and an amount of data (such as a number of LBA quanta, e.g., sectors) to write; in response the SSD provides write status and/or requests write data and optionally subsequently provides write status. For yet another example, the commands include a de-allocation command (e.g. a trim command) specifying one or more addresses (such as one or more LBAs) that no longer need be allocated; in response the SSD modifies the Map accordingly and optionally provides de-allocation status. In some contexts an ATA compatible TRIM command is an exemplary de-allocation command. For yet another example, the commands include a super capacitor test command or a data hardening success query; in response, the SSD provides appropriate status. In some embodiments, Host Interfaces 111 is compatible with a SATA protocol and, using NCQ commands, is enabled to have up to 32 pending commands, each with a unique tag represented as a number from 0 to 31. In some embodiments, Tag Tracking 113 is enabled to associate an external tag for a command received via External Interfaces 110 with an internal tag used to track the command during processing by SSD Controller 100.

According to various embodiments, one or more of: Data Processing 121 optionally and/or selectively processes some or all data sent between Buffer 131 and External Interfaces 110; and Data Processing 121 optionally and/or selectively processes data stored in Buffer 131. In some embodiments, Data Processing 121 uses one or more Engines 123 to perform one or more of: formatting; reformatting; transcoding; and any other data processing and/or manipulation task.

Buffer 131 stores data sent to/from External Interfaces 110 from/to Device Interfaces 190. In some embodiments, Buffer 131 additionally stores system data, such as some or all map tables, used by SSD Controller 100 to manage one or more of Flash Device 192. In various embodiments, Buffer 131 has one or more of: Memory 137 used for temporary storage of data; DMA 133 used to control movement of data to and/or from Buffer 131; and ECC-X 135 used to provide higher-level error correction and/or redundancy functions; and other data movement and/or manipulation functions. An example of a higher-level redundancy function is a RAID-like capability, where redundancy is at a flash device (e.g., multiple ones of Flash Device 192) level and/or a flash die (e.g., Flash Die 194) level instead of at a disk level.

According to various embodiments, one or more of: ECC 161 optionally and/or selectively processes some or all data sent between Buffer 131 and Device Interfaces 190; and ECC 161 optionally and/or selectively processes data stored in Buffer 131. In some embodiments, ECC 161 is used to provide lower-level error correction and/or redundancy functions, such as in accordance with one or more ECC techniques. In some embodiments, ECC 161 implements one or more of: a CRC code; a Hamming code; an RS code; a BCH code; an LDPC code; a Viterbi code; a trellis code; a hard-decision code; a soft-decision code; an erasure-based code; any error detecting and/or correcting code; and any combination of the preceding. In some embodiments, ECC 161 includes one or more decoders (such as LDPC decoders).

Device Interface Logic 191 controls instances of Flash Device 192 via Device Interfaces 190. Device Interface Logic 191 is enabled to send data to/from the instances of Flash Device 192 according to a protocol of Flash Device 192. Device Interface Logic 191 includes Scheduling 193 to selectively sequence control of the instances of Flash Device 192 via Device Interfaces 190. For example, in some embodiments, Scheduling 193 is enabled to queue operations to the instances of Flash Device 192, and to selectively send the operations to individual ones of the instances of Flash Device 192 (or Flash Die 194) as individual ones of the instances of Flash Device 192 (or Flash Die 194) are available.

Map 141 converts between data addressing used on External Interfaces 110 and data addressing used on Device Interfaces 190, using Table 143 to map external data addresses to locations in NVM 199. For example, in some embodiments, Map 141 converts LBAs used on External Interfaces 110 to block and/or page addresses targeting one or more Flash Die 194, via mapping provided by Table 143. For LBAs that have never been written since drive manufacture or de-allocation, the Map points to a default value to return if the LBAs are read. For example, when processing a de-allocation command, the Map is modified so that entries corresponding to the de-allocated LBAs point to one of the default values. In various embodiments, there are various default values, each having a corresponding pointer. The plurality of default values enables reading some de-allocated LBAs (such as in a first range) as one default value, while reading other de-allocated LBAs (such as in a second range) as another default value. The default values, in various embodiments, are defined by flash memory, hardware, firmware, command and/or primitive arguments and/or parameters, programmable registers, or various combinations thereof.

In some embodiments, Map 141 uses Table 143 to perform and/or to look up translations between addresses used on External Interfaces 110 and data addressing used on Device Interfaces 190. According to various embodiments, Table 143 is one or more of: a one-level map; a two-level map; a multi-level map; a map cache; a compressed map; any type of mapping from one address space to another; and any combination of the foregoing. According to various embodiments, Table 143 includes one or more of: static random access memory; dynamic random access memory; NVM (such as flash memory); cache memory; on-chip memory; off-chip memory; and any combination of the foregoing.

In some embodiments, Recycler 151 performs garbage collection. For example, in some embodiments, instances of Flash Device 192 contain blocks that must be erased before the blocks are re-writeable. Recycler 151 is enabled to determine which portions of the instances of Flash Device 192 are actively in use (e.g., allocated instead of de-allocated), such as by scanning a map maintained by Map 141, and to make unused (e.g., de-allocated) portions of the instances of Flash Device 192 available for writing by erasing them. In further embodiments, Recycler 151 is enabled to move data stored within instances of Flash Device 192 to make larger contiguous portions of the instances of Flash Device 192 available for writing.

In some embodiments, instances of Flash Device 192 are selectively and/or dynamically configured, managed, and/or used to have one or more bands for storing data of different types and/or properties. A number, arrangement, size, and type of the bands are dynamically changeable. For example, data from a computing host is written into a hot (active) band, while data from Recycler 151 is written into a cold (less active) band. In some usage scenarios, if the computing host writes a long, sequential stream, then a size of the hot band grows, whereas if the computing host does random writes or few writes, then a size of the cold band grows.

CPU 171 controls various portions of SSD Controller 100. CPU 171 includes CPU Core 172. CPU Core 172 is, according to various embodiments, one or more single-core or multi-core processors. The individual processors cores in CPU Core 172 are, in some embodiments, multi-threaded. CPU Core 172 includes instruction and/or data caches and/or memories. For example, the instruction memory contains instructions to enable CPU Core 172 to execute programs (e.g. software sometimes called firmware) to control SSD Controller 100. In some embodiments, some or all of the firmware executed by CPU Core 172 is stored on instances of Flash Device 192 (as illustrated, e.g., as Firmware 106 of NVM 199 in FIG. 1B).

In various embodiments, CPU 171 further includes: Command Management 173 to track and control commands received via External Interfaces 110 while the commands are in progress; Buffer Management 175 to control allocation and use of Buffer 131; Translation Management 177 to control Map 141; Coherency Management 179 to control consistency of data addressing and to avoid conflicts such as between external data accesses and recycle data accesses; Device Management 181 to control Device Interface Logic 191; Identity Management 182 to control modification and communication of identify information, and optionally other management units. None, any, or all of the management functions performed by CPU 171 are, according to various embodiments, controlled and/or managed by hardware, by software (such as firmware executing on CPU Core 172 or on a host connected via External Interfaces 110), or any combination thereof.

In some embodiments, CPU 171 is enabled to perform other management tasks, such as one or more of: gathering and/or reporting performance statistics; implementing SMART; controlling power sequencing, controlling and/or monitoring and/or adjusting power consumption; responding to power failures; controlling and/or monitoring and/or adjusting clock rates; and other management tasks.

Various embodiments include a computing-host flash memory controller that is similar to SSD Controller 100 and is compatible with operation with various computing hosts, such as via adaptation of Host Interfaces 111 and/or External Interfaces 110. The various computing hosts include one or any combination of a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, a netbook computer, a tablet device or computer, an ultrabook computer, an electronic reading device (such as an e-reader), a PDA, a navigation system, a (handheld) GPS device, an automotive control system, an automotive media control system or computer, a printer, copier or fax machine or all-in-one device, a POS device, a cash-register, a media player, a television, a media recorder, a DVR, a digital camera, a cellular handset, a cordless telephone handset, and an electronic game.

In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller) are implemented on a single IC, a single die of a multi-die IC, a plurality of dice of a multi-die IC, or a plurality of ICs. For example, Buffer 131 is implemented on a same die as other elements of SSD Controller 100. For another example, Buffer 131 is implemented on a different die than other elements of SSD Controller 100.

FIG. 1B illustrates selected details of various embodiments of systems including one or more instances of the SSD of FIG. 1A. SSD 101 includes SSD Controller 100 coupled to NVM 199 via Device Interfaces 190. The figure illustrates various classes of embodiments: a single SSD coupled directly to a host, a plurality of SSDs each respectively coupled directly to a host via respective external interfaces, and one or more SSDs coupled indirectly to a host via various interconnection elements.

As an example embodiment of a single SSD coupled directly to a host, one instance of SSD 101 is coupled directly to Host 102 via External Interfaces 110 (e.g. Switch/Fabric/Intermediate Controller 103 is omitted, bypassed, or passed-through). As an example embodiment of a plurality of SSDs each coupled directly to a host via respective external interfaces, each of a plurality of instances of SSD 101 is respectively coupled directly to Host 102 via a respective instance of External Interfaces 110 (e.g. Switch/Fabric/Intermediate Controller 103 is omitted, bypassed, or passed-through). As an example embodiment of one or more SSDs coupled indirectly to a host via various interconnection elements, each of one or more instances of SSD 101 is respectively coupled indirectly to Host 102. Each indirect coupling is via a respective instance of External Interfaces 110 coupled to Switch/Fabric/Intermediate Controller 103, and Intermediate Interfaces 104 coupling to Host 102.

Some of the embodiments including Switch/Fabric/Intermediate Controller 103 also include Card Memory 112C coupled via Memory Interface 180 and accessible by the SSDs. In various embodiments, one or more of the SSDs, the Switch/Fabric/Intermediate Controller, and/or the Card Memory are included on a physically identifiable module, card, or pluggable element (e.g. I/O Card 116). In some embodiments, SSD 101 (or variations thereof) corresponds to a SAS drive or a SATA drive that is coupled to an initiator operating as Host 102.

Host 102 is enabled to execute various elements of Host Software 115, such as various combinations of OS 105, Driver 107, Application 109, and Multi-Device Management Software 114. Dotted-arrow 107D is representative of Host Software←→I/O Device Communication, e.g. data sent/received to/from one or more of the instances of SSD 101 and from/to any one or more of OS 105 via Driver 107, Driver 107, and Application 109, either via Driver 107, or directly as a VF.

OS 105 includes and/or is enabled to operate with drivers (illustrated conceptually by Driver 107) for interfacing with the SSD. Various versions of Windows (e.g. 95, 98, ME, NT, XP, 2000, Server, Vista, and 7), various versions of Linux (e.g. Red Hat, Debian, and Ubuntu), and various versions of MacOS (e.g. 8, 9 and X) are examples of OS 105. In various embodiments, the drivers are standard and/or generic drivers (sometimes termed “shrink-wrapped” or “pre-installed”) operable with a standard interface and/or protocol such as SATA, AHCI, or NVM Express, or are optionally customized and/or vendor specific to enable use of commands specific to SSD 101. Some drives and/or drivers have pass-through modes to enable application-level programs, such as Application 109 via Optimized NAND Access (sometimes termed ONA) or Direct NAND Access (sometimes termed DNA) techniques, to communicate commands directly to SSD 101, enabling a customized application to use commands specific to SSD 101 even with a generic driver. ONA techniques include one or more of: use of non-standard modifiers (hints); use of vendor-specific commands; communication of non-standard statistics, such as actual NVM usage according to compressibility; and other techniques. DNA techniques include one or more of: use of non-standard commands or vendor-specific providing unmapped read, write, and/or erase access to the NVM; use of non-standard or vendor-specific commands providing more direct access to the NVM, such as by bypassing formatting of data that the I/O device would otherwise do; and other techniques. Examples of the driver are a driver without ONA or DNA support, an ONA-enabled driver, a DNA-enabled driver, and an ONA/DNA-enabled driver. Further examples of the driver are a vendor-provided, vendor-developed, and/or vendor-enhanced driver, and a client-provided, client-developed, and/or client-enhanced driver.

Examples of the application-level programs are an application without ONA or DNA support, an ONA-enabled application, a DNA-enabled application, and an ONA/DNA-enabled application. Dotted-arrow 109D is representative of Application←→I/O Device Communication (e.g. bypass via a driver or bypass via a VF for an application), e.g. an ONA-enabled application and an ONA-enabled driver communicating with an SSD, such as without the application using the OS as an intermediary. Dotted-arrow 109V is representative of Application←→I/O Device Communication (e.g. bypass via a VF for an application), e.g. a DNA-enabled application and a DNA-enabled driver communicating with an SSD, such as without the application using the OS or the driver as intermediaries.

One or more portions of NVM 199 are used, in some embodiments, for firmware storage, e.g. Firmware 106. The firmware storage includes one or more firmware images (or portions thereof). A firmware image has, for example, one or more images of firmware, executed, e.g., by CPU Core 172 of SSD Controller 100. A firmware image has, for another example, one or more images of constants, parameter values, and NVM device information, referenced, e.g. by the CPU core during the firmware execution. The images of firmware correspond, e.g., to a current firmware image and zero or more previous (with respect to firmware updates) firmware images. In various embodiments, the firmware provides for generic, standard, ONA, and/or DNA operating modes. In some embodiments, one or more of the firmware operating modes are enabled (e.g. one or more APIs are “unlocked”) via keys or various software techniques, optionally communicated and/or provided by a driver.

In some embodiments lacking the Switch/Fabric/Intermediate Controller, the SSD is coupled to the Host directly via External Interfaces 110. In various embodiments, SSD Controller 100 is coupled to the Host via one or more intermediate levels of other controllers, such as a RAID controller. In some embodiments, SSD 101 (or variations thereof) corresponds to a SAS drive or a SATA drive and Switch/Fabric/Intermediate Controller 103 corresponds to an expander that is in turn coupled to an initiator, or alternatively Switch/Fabric/Intermediate Controller 103 corresponds to a bridge that is indirectly coupled to an initiator via an expander. In some embodiments, Switch/Fabric/Intermediate Controller 103 includes one or more PCIe switches and/or fabrics.

In various embodiments, such as some of the embodiments where Host 102 is a computing host (e.g. a computer, a workstation computer, a server computer, a storage server, a SAN, a NAS device, a DAS device, a storage appliance, a PC, a laptop computer, a notebook computer, and/or a netbook computer), the computing host is optionally enabled to communicate (e.g. via optional I/O & Storage Devices/Resources 117 and optional LAN/WAN 119) with one or more local and/or remote servers (e.g. optional Servers 118). The communication enables, for example, local and/or remote access, management, and/or usage of any one or more of SSD 101 elements. In some embodiments, the communication is wholly or partially via Ethernet. In some embodiments, the communication is wholly or partially via Fibre Channel. LAN/WAN 119 is representative, in various embodiments, of one or more Local and/or Wide Area Networks, such as any one or more of a network in a server farm, a network coupling server farms, a metro-area network, and the Internet.

In various embodiments, an SSD controller and/or a computing-host flash memory controller in combination with one or more NVMs are implemented as a non-volatile storage component, such as a USB storage component, a CF storage component, an MMC storage component, an eMMC storage component, a Thunderbolt storage component, a UFS storage component, an SD storage component, a Memory Stick storage component, and an xD-picture card storage component.

In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller), or functions thereof, are implemented in a host that the controller is to be coupled with (e.g., Host 102 of FIG. 1B). In various embodiments, all or any portions of an SSD controller (or a computing-host flash memory controller), or functions thereof, are implemented via hardware (e.g., logic circuitry), software and/or firmware (e.g., driver software or SSD control firmware), or any combination thereof. For example, functionality of or associated with an ECC unit (such as similar to ECC 161 and/or ECC-X 135 of FIG. 1A) is implemented partially via software on a host and partially via a combination of firmware and hardware in an SSD controller. For another example, functionality of or associated with a recycler unit (such as similar to Recycler 151 of FIG. 1A) is implemented partially via software on a host and partially via hardware in a computing-host flash memory controller.

Decoding of a Non-Volatile Memory (NVM)

FIGS. 2A and 2B illustrate device threshold voltage distributions relevant to decoding of an NVM, specifically respectively for SLC and MLC memories. For the purposes of this discussion, each hill-like bump is an abstraction for an independent Gaussian-like curve representing a device threshold voltage probability distribution for a respective state of a read unit sized portion of an NVM. The device threshold voltage axis is drawn with increasing positive voltage to the right. An absolute scale is purposefully not provided, and no reference points are identified, such that the plots apply more generally to a larger population of NVMs.

In FIG. 2A, leftmost distribution 220 represents a logical one and the rightmost distribution 230 represents a logical zero. Depending on the technology, the leftmost distribution may reside (at least predominantly) at negative voltages. Read threshold 210 is ideally situated between the two distributions.

Except as linked by the embodiments herein, independent of these device threshold voltage distributions, in some embodiments, the NVM is written with specific knowledge of the statistical distribution of zeroes and ones being stored. More particularly, in some embodiments various encryption and/or scrambling techniques are used such that the statistical distribution of zeroes and ones is 50-50 percent (50 percent zeroes and 50 percent ones). When the SLC is read using the nominal read threshold, which is ideally situated for the case of FIG. 2A, the observed read data statistical distribution of zeroes and ones is likewise 50-50 percent. The statistical distribution being 50-50 percent does not mean that any one sample of data would have an exactly even balance of zero bits and one bits, but rather that an average over many samples produces a ratio of zero bits and one bits that converges on 50-50 percent with an increasingly tight probabilistic bound as a number of the samples increases. An analogy is a distribution of heads and tails when a coin is flipped many times, generating a Gaussian distribution with a variance that is approximated by n/4 where n is a number of the coin flips. For example, if there are 18,432 bits in a read unit with a 50-50 percent statistical distribution of zero bits and one bits, the variance in the number of zero bits (or one bits) is approximately 4,608 and the standard deviation is approximately 68. With a standard deviation of 68, less than one in one million samples of read units would be expected to have a number of zero bits more than 340 (5 standard deviations) away from the average of 9,216.

Similarly, FIG. 2B represents device threshold voltage distributions. More specifically, for a selected Gray code mapping, device threshold voltage distributions 250, 260, 270, and 280 represent four discrete states. Three read thresholds are also shown: V_(READ1) 240, V_(READ2) 242, and V_(READ3) 244. Again for the purposes of example, each of the three read thresholds is situated between two adjacent distributions and serves to distinguish between the four discrete states.

In some embodiments, various scrambling techniques are used such that the statistical distribution of the four states is 25-25-25-25 percent (25 percent in each state). When the MLC is read using the nominal read thresholds that are ideally situated for the case of FIG. 2B, in some embodiments the statistical distribution of the four states is configurable to likewise be 25-25-25-25 percent. (As discussed elsewhere, zeroes and ones are directly observable by the controller, but all four states are inferable as required.)

Functions for Decoding of a Non-Volatile Memory (NVM)

FIG. 3 provides alternate views of SSD 101, SSD Controller 100, and NVM 199 of FIGS. 1A and 1B, redrawing selected logic block boundaries to emphasize particular functions. SSD 101 at the top level features External Interfaces 110, SSD Controller 100, NVM 199, and Device Interface 190.

External Interfaces 110 is coupled to a host, such as Host 102 of FIG. 1B, and supports a high-level storage protocol such as SATA, including host-sourced storage-related commands and write-data and controller-sourced read-data, and as detailed in the above discussion of FIG. 1A. Device Interface 190 supports low-level NVM I/O transactions, as detailed in the discussion of FIG. 1A. NVM 199 features NVM Array 332, Programmable Read Voltage Circuitry 334, Control/Status Registers 336, and I/O 338. SSD Controller 100 features Host Interfaces 111, Scrambler 310, ECC/LDPC Encoder 320, Device Interface Logic 191, Channel Parameter Estimator 340, Buffer 131, ECC/LDPC Decoder 360, Descrambler 370, and Soft Metric Converter 380. Host Interfaces 111 couples with the Host via External Interfaces 110 as discussed elsewhere herein, provides Write Data 306 to Scrambler 310, and receives Read Data 351 from Buffer 131.

The write path and functionality are as follows. Scrambler 310 operates on Write Data 306 to generate Scrambled Write Data 311 to ECC/LDPC Encoder 320. Scrambler 310 scrambles Write Data 306 in a reversible manner and such that the Scrambled Write Data 311 has a known statistical distribution of states stored. An example of a block including scrambled data is a block containing Scrambled Write Data 311. E.g. an SLC block including scrambled data contains an equal number of ‘0’ and ‘1’ values and a 4LC block including scrambled data contains an equal number of ‘00’, ‘01’, ‘10’, and ‘11’ states. In some embodiments, Scrambler 310 performs encryption, such as via an AES encoder that randomizes the data as a by-product of encryption. In some embodiments, Scrambler 310 uses a Linear Feedback Shift Register (LFSR) to randomize the data (but without any data security intent). ECC/LDPC Encoder 320 processes the Scrambled Write Data 311 to add additional error correction bits (e.g. ECC and/or LDPC), resulting in ECC Encoded Write Data 321 that is provided to Device Interface 191 for storing into NVM 199 via Device Interface 190.

The basic read path and functionality are as follows. NVM pages, including Uncorrected and Scrambled (Raw) Read Data 359, are received from NVM 199 via Device Interface 190. Continuing with respect to FIG. 3, each read unit nominally includes the data scrambled by Scrambler 301 as well as the additional error correction bits generated by ECC/LDPC Encoder 320, but as generally unintentionally altered as a result of NVM storage and retrieval operations. The read units are provided to ECC/LDPC Decoder 360 via Buffer 131. ECC/LDPC Decoder 360 processes the read units, exploiting the included additional error correction bits to generally correct any errors that may have arisen at any point and time since the data was first encoded, resulting in Corrected Read Data 361 that is provided to Descrambler 370. Descrambler 370 operates on Corrected Read Data 361, reversing the scrambling performed by Scrambler 310, resulting in Unscrambled Read Data 371 that is provided at least in part as Read Data 351 to Host Interfaces 111 via Buffer 131.

The read path and functionality further includes Channel Parameter Estimator 340 and Soft Metric Converter 380. Channel Parameter Estimator 340 monitors Raw Read Data 359 received from the NVM, and estimates Channel Parameters 341. Examples of the Channel Parameters include any one or more of: cell device threshold voltage distributions (e.g., any one or more parameters, such as mean and standard deviation, of any one or more distributions of any one or more of the charge states) and read thresholds (e.g., any one or more read thresholds). Soft Metric Converter 380 receives the Channel Parameters and hard-decision read data (via Device Interface Logic 191). and generates Soft Metrics 362 (a.k.a. soft-decision criteria). Soft Metrics are used by the ECC/LPDC Encoder for soft-decoding (e.g. LDPC decoding) to retrieve Corrected Read Data.

FIG. 3 illustrates functions for decoding of an NVM in a context where a host operates as a source and a sink for data written to and read from NVM 199. In various embodiments (such as illustrated by FIG. 1A and FIG. 1B), one or more other agents operate as sources and sinks for data written to and read from NVM 199. An example of the other agents is Recycler 151 of FIG. 1A, that moves data from one location to another in NVM 199, as described elsewhere herein.

In various embodiments, any or all portions of functionality associated with any one or more of Scrambler 310, ECC/LDPC Encoder 320, ECC/LDPC Decoder 360, and Descrambler 370 are implemented at least in part using one or more of Data Processing 121 and ECC 161 (both of FIG. 1A).

Soft-Decision Decoding of Non-Volatile Memory (NVM)

FIG. 4 illustrates a flow diagram of selected details of an embodiment of single-read based soft-decision decoding of NVM. To retrieve data stored at one or more locations of an NVM (e.g. a flash memory), a controller requests the NVM to read the locations 410. In response, the NVM performs N array accesses of each of one or more non-volatile (e.g. flash) cells of the NVM, each of the array accesses in accordance with a respective read threshold, and the cells corresponding to the locations. In an SLC, such as an SLC flash memory technique (e.g., as illustrated in FIG. 2A), a cell has two discrete states and N is one. In an MLC, such as an MLC flash memory technique, a cell has more than two discrete states and N is one or more. In some embodiments, a 2-bit per cell MLC (e.g., as illustrated in FIG. 2B), has four states and N is three. In other embodiments, a 3-bit per cell MLC has eight states and N is seven.

The raw read data (e.g. Uncorrected and Scrambled (Raw) Read Data 359 of FIG. 3) obtained from the non-volatile (e.g. flash) cells via the array accesses is received via interface hardware (e.g. Device Interface Logic 191 of FIG. 3). The raw read data is decoded by the controller to obtain the stored data. In various embodiments, the raw read data is hard decoded 420 to obtain the stored data. In some embodiments, the decoding is performed by various hardware elements (e.g. any one or more of Buffer 131, ECC/LDPC Decoder 360, and Descrambler 370 of FIG. 3). The controller detects whether an uncorrectable error has occurred 430. In some embodiments and/or scenarios, the error detection is performed by at least an ECC decoder (e.g., using a BCH code via ECC/LDPC Decoder 360 of FIG. 3). If no uncorrectable error has occurred, then the read by the controller has successfully retrieved the stored data and the controller may issue another read.

In some embodiments and/or scenarios, if an uncorrectable error has occurred, the controller attempts to soft decode the raw read data. Soft decoding algorithms (e.g., LDPC) have higher error correction capabilities than hard decoding, but are more computationally expensive. In various scenarios, soft decoding correctly retrieves the stored data, even if hard decoding resulted in an uncorrectable error. In various embodiments, soft-decision metrics are generated 440 for soft decoding. In some scenarios of soft decoding, the controller requests one or more additional reads of the NVM and in response the NVM performs N or more array accesses. The controller receives additional raw data, corresponding to the one or more additional reads, and generates soft-decision metrics and/or performs soft decoding using the additional raw read data.

In some embodiments, the controller generates soft-decision metrics using Channel Parameters 450, based at least in part on and/or in conjunction with at least some results of Read NVM Location 410, instead of performing additional reads and/or additional array accesses. In various embodiments, examples of the Channel Parameters are any one or more of: cell device threshold voltage distributions (e.g., any one or more parameters, such as mean and standard deviation, of any one or more distributions of any one or more of the charge states) and read thresholds (e.g., any one or more read thresholds). The soft-decision metrics are generated in accordance with Equations 1.1-1.4 (Equations 1.1-1.6 are described in Appendix “Selected Details of Particular Embodiments of Single-Read Based Soft-decision Decoding of Non-Volatile Memory (NVM)” attached, and incorporated herein by reference for all purposes). Equations 1.1, 1.2, 1.3, and 1.4 respectively describe the soft-decision metrics for decoding a lower page one, a lower page zero, an upper page one, and an upper page zero in an MLC memory. Equations 1.5 and 1.6 respectively describe the soft-decision metrics for decoding a lower page one and a lower page zero, calculated using the Channel Parameters (e.g., mean and standard deviation for a Gaussian-approximated charge distribution and read threshold) in an MLC memory.

The raw read data from Read NVM Location 410 is soft decoded 460, based on the generated soft-decision metrics. In various embodiments and/or scenarios, the soft decoding successfully retrieves the stored data. Generating the soft-decision metrics using Channel Parameters 450, based at least in part on and/or in conjunction with at least some results of Read NVM Location 410, eliminates the one or more additional reads and N or more array accesses, thus enhancing operation by one or more of reducing power consumption, read latency, cell fatigue, controller utilization, and improving available array bandwidth.

APPENDIX Selected Details of Particular Embodiments of Single-Read Based Soft-Decision Decoding of Non-Volatile Memory (NVM)

An Appendix entitled “Selected Details of Particular Embodiments of Single-Read Based Soft-Decision Decoding of Non-Volatile Memory (NVM)” is attached to this application and is incorporated by reference herein for all purposes in this application. The Appendix describes, for example, Equations 1.1-1.6, referred to elsewhere herein.

Example Implementation Techniques

In some embodiments, various combinations of all or portions of operations performed by an SSD using single-read based soft-decision decoding of NVM, e.g., with flash memories, a computing-host flash memory controller, and/or an SSD controller (such as SSD Controller 100 of FIG. 1A), and portions of a processor, microprocessor, system-on-a-chip, application-specific-integrated-circuit, hardware accelerator, or other circuitry providing all or portions of the aforementioned operations, are specified by a specification compatible with processing by a computer system. The specification is in accordance with various descriptions, such as hardware description languages, circuit descriptions, netlist descriptions, mask descriptions, or layout descriptions. Example descriptions include: Verilog, VHDL, SPICE, SPICE variants such as PSpice, IBIS, LEF, DEF, GDS-II, OASIS, or other descriptions. In various embodiments, the processing includes any combination of interpretation, compilation, simulation, and synthesis to produce, to verify, or to specify logic and/or circuitry suitable for inclusion on one or more integrated circuits. Each integrated circuit, according to various embodiments, is designable and/or manufacturable according to a variety of techniques. The techniques include a programmable technique (such as a field or mask programmable gate array integrated circuit), a semi-custom technique (such as a wholly or partially cell-based integrated circuit), and a full-custom technique (such as an integrated circuit that is substantially specialized), any combination thereof, or any other technique compatible with design and/or manufacturing of integrated circuits.

In some embodiments, various combinations of all or portions of operations as described by a computer readable medium having a set of instructions stored therein, are performed by execution and/or interpretation of one or more program instructions, by interpretation and/or compiling of one or more source and/or script language statements, or by execution of binary instructions produced by compiling, translating, and/or interpreting information expressed in programming and/or scripting language statements. The statements are compatible with any standard programming or scripting language (such as C, C++, Fortran, Pascal, Ada, Java, VBscript, and Shell). One or more of the program instructions, the language statements, or the binary instructions, are optionally stored on one or more computer readable storage medium elements. In various embodiments, some, all, or various portions of the program instructions are realized as one or more functions, routines, sub-routines, in-line routines, procedures, macros, or portions thereof.

CONCLUSION

Certain choices have been made in the description merely for convenience in preparing the text and drawings and unless there is an indication to the contrary the choices should not be construed per se as conveying additional information regarding structure or operation of the embodiments described. Examples of the choices include: the particular organization or assignment of the designations used for the figure numbering and the particular organization or assignment of the element identifiers (the callouts or numerical designators, e.g.) used to identify and reference the features and elements of the embodiments.

The words “includes” or “including” are specifically intended to be construed as abstractions describing logical sets of open-ended scope and are not meant to convey physical containment unless explicitly followed by the word “within.”

Although the foregoing embodiments have been described in some detail for purposes of clarity of description and understanding, the invention is not limited to the details provided. There are many embodiments of the invention. The disclosed embodiments are exemplary and not restrictive.

It will be understood that many variations in construction, arrangement, and use are possible consistent with the description, and are within the scope of the claims of the issued patent. For example, interconnect and function-unit bit-widths, clock speeds, and the type of technology used are variable according to various embodiments in each component block. The names given to interconnect and logic are merely exemplary, and should not be construed as limiting the concepts described. The order and arrangement of flowchart and flow diagram process, action, and function elements are variable according to various embodiments. Also, unless specifically stated to the contrary, value ranges specified, maximum and minimum values used, or other particular specifications (such as flash memory technology types; and the number of entries or stages in registers and buffers), are merely those of the described embodiments, are expected to track improvements and changes in implementation technology, and should not be construed as limitations.

Functionally equivalent techniques known in the art are employable instead of those described to implement various components, sub-systems, operations, functions, routines, sub-routines, in-line routines, procedures, macros, or portions thereof. It is also understood that many functional aspects of embodiments are realizable selectively in either hardware (e.g., generally dedicated circuitry) or software (e.g., via some manner of programmed controller or processor), as a function of embodiment dependent design constraints and technology trends of faster processing (facilitating migration of functions previously in hardware into software) and higher integration density (facilitating migration of functions previously in software into hardware). Specific variations in various embodiments include, but are not limited to: differences in partitioning; different form factors and configurations; use of different operating systems and other system software; use of different interface standards, network protocols, or communication links; and other variations to be expected when implementing the concepts described herein in accordance with the unique engineering and business constraints of a particular application.

The embodiments have been described with detail and environmental context well beyond that required for a minimal implementation of many aspects of the embodiments described. Those of ordinary skill in the art will recognize that some embodiments omit disclosed components or features without altering the basic cooperation among the remaining elements. It is thus understood that much of the details disclosed are not required to implement various aspects of the embodiments described. To the extent that the remaining elements are distinguishable from the prior art, components and features that are omitted are not limiting on the concepts described herein.

All such variations in design are insubstantial changes over the teachings conveyed by the described embodiments. It is also understood that the embodiments described herein have broad applicability to other computing and networking applications, and are not limited to the particular application or industry of the described embodiments. The invention is thus to be construed as including all possible modifications and variations encompassed within the scope of the claims of the issued patent. 

What is claimed is:
 1. A method comprising: in a controller configured to operate with a Non-Volatile Memory (NVM), controlling a single read of a location of the NVM in response to a request from a host received via a host interface of the controller; in the controller, hard-decoding data from the single read of the location of the NVM to determine whether the single read of the location of the NVM resulted in a read error; in the controller, using information from solely the single read of the location of the NVM to generate soft-decision metrics if it is determined the single read of the location of the NVM resulted in a read error; and performing soft-decision decoding to determine contents of the location based at least in part on the generated soft-decision metrics.
 2. The method of claim 1, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.
 3. The method of claim 1, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.
 4. The method of claim 3, wherein the channel parameters are particular channel parameters, various channel parameters comprise the particular channel parameters and one or more other channel parameters, and further comprising computing the various channel parameters as respective channel parameters for each of a plurality of regions of the NVM, the location being in a particular one of the regions.
 5. The method of claim 3, wherein the controller estimates the device threshold voltage distributions.
 6. The method of claim 1, wherein the controller comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a Solid State Disk (SSD).
 7. The method of claim 1, wherein the controller comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a single Integrated Circuit (IC).
 8. A tangible non-transitory computer readable medium having a set of instructions stored therein that when executed by a processing element of a controller configured to operate with a Non-Volatile Memory (NVM) cause the processing element to perform and/or control operations comprising: controlling a single read of a location of the NVM in response to a request from a host received via a host interface of the controller; hard-decoding data from the single read of the location of the NVM to determine whether the single read of the location of the NVM resulted in a read error; using information from solely a single read of the location of the NVM to generate soft-decision metrics if it is determined the single read of the location of the NVM resulted in a read error; and performing soft-decision decoding to determine contents of the location based at least in part on the generated soft-decision metrics.
 9. The tangible non-transitory computer readable medium of claim 8, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.
 10. The tangible non-transitory computer readable medium of claim 8, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.
 11. The tangible non-transitory computer readable medium of claim 10, wherein the channel parameters are particular channel parameters, various channel parameters comprise the particular channel parameters and one or more other channel parameters, and the operations further comprise computing the various channel parameters as respective channel parameters for each of a plurality of regions of the NVM, the location being in a particular one of the regions.
 12. The tangible non-transitory computer readable medium of claim 10, wherein the operations further comprise estimating the device threshold voltage distributions.
 13. The tangible non-transitory computer readable medium of claim 8, wherein the processing element is comprised in a controller that comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a Solid State Disk (SSD).
 14. The tangible non-transitory computer readable medium of claim 8, wherein the processing element is comprised in a controller that comprises a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host, the controller further comprises a flash memory interface enabled to communicate with at least one flash memory of the NVM, and the controller is comprised in a single Integrated Circuit (IC).
 15. An apparatus comprising: a host interface that is compatible with at least one storage interface standard and enabled to communicate with a host; read circuitry configured to control a single read of a location of the NVM in response to a request from a host received via a host interface of the controller; hard-decision decoding logic circuitry configured to hard-decode data from the single read of the location of the NVM to determine whether the single read of the location of the NVM resulted in a read error; soft metric conversion hardware logic circuitry enabled to use information from solely a single read of the location of the NVM to generate soft-decision metrics if it is determined the single read of the location of the NVM resulted in a read error; and soft-decision decoding hardware logic circuitry enabled to perform soft-decision decoding to determine contents of the location based at least in part on the generated soft-decision metrics.
 16. The apparatus of claim 15, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.
 17. The apparatus of claim 15, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.
 18. The apparatus of claim 17, further comprising device threshold voltage estimation hardware logic circuitry enabled to estimate the device threshold voltage distributions.
 19. The apparatus of claim 15, further comprising: a flash memory interface enabled to communicate with at least one flash memory of the NVM; and wherein the soft metric conversion hardware logic circuitry, the soft-decision decoding hardware logic circuitry, the host interface, and the flash memory interface are comprised in a Solid State Disk (SSD).
 20. The apparatus of claim 15, further comprising: a flash memory interface enabled to communicate with at least one flash memory of the NVM; and wherein the soft metric conversion hardware logic circuitry, the soft-decision decoding hardware logic circuitry, the host interface, and the flash memory interface are comprised in a single Integrated Circuit (IC).
 21. A system comprising: means for controlling a single read of a location of the NVM in response to a request from a host received via a host interface of the controller; means for hard-decoding data from the single read of the location of the NVM to determine whether the single read of the location of the NVM resulted in a read error; means for using information from solely the single read of the location of the NVM to generate soft-decision metrics if it is determined the single read of the location of the NVM resulted in a read error; and means for performing soft-decision decoding to determine contents of the location based at least in part on the generated soft-decision metrics.
 22. The system of claim 21, wherein the location is operated in accordance with a Multi-Level Cell (MLC) technique providing N discrete states, and the single read corresponds to less than N array accesses of at least the location, each of the array accesses in accordance with a respective read threshold.
 23. The system of claim 21, wherein the generating of the soft-decision metrics is based at least in part on channel parameters of the location, the channel parameters comprising any one or more of one or more device threshold voltage distributions and one or more operating read thresholds.
 24. The system of claim 23, further comprising means for estimating the device threshold voltage distributions. 